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1 description ltc 2123, ltc 2122 14-bit, 250msps to 170msps dual adcs with jesd204b outputs demonstration circuit 1974 supports the lt c ? 2123 14-bit dual adc family with jesd204b compliant cml outputs. it was specially designed for applications that require single- ended ac coupled inputs. the dc1974 supports the LTC2123 and ltc2122 with sample rates from 250msps to 170msps. the specific adc characteristics are listed in the dc1974 variants section. the circuitry on the analog inputs is opti - mized for analog input frequencies from 5mhz to 400mhz. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and pscope is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. refer to the data sheet for proper input networks for dif - ferent input frequencies. design files for this circuit board are available at http://www .linear.com/demo/dc1974 dc1974 variants adc part number resolution (bit) maximum sample rate (msps) input frequency (mhz) 1974a-b LTC2123 14 250 5 to 400 1974a-c ltc2122 14 170 5 to 400 parameter condition min typ max unit adc supply voltage this supply must provide up to 700ma 4 6 v analog input range 1.35 1.5 v pp sampling frequency (device clock frequency) depending on adc (1x clk mode) 10 250 mhz device clock level (single-ended at j3) minimum logic levels (dev clk + tied to gnd) 0 v maximum logic levels (dev clk + tied to gnd) 3.6 v device clock level (differential signal across j3 and j4) minimum logic levels (dev clk + not tied to gnd, 1.2v common mode) 0.2 v digital inputs (adc_sys_ref_n, adc_sys_ref_p, sync_n, sync_p) differential input voltage 0.2 1.8 v common mode input range 1.1 1.2 1.5 v performance summary specifications are at t a = 25c dc1974 variants dc1974fa demo manual dc1974
2 quick start procedure figure 1. dc1974 setup demonstration circuit 1974 is easy to set up to evaluate the performance of the LTC2123 a/d converter family. refer to figure 1 for proper measurement equipment setup and follow the procedure below: setup the dc 1974 evaluation system uses standard , off the shelf fpga evaluation boards for data capture and communi - cation with the host computer. follow the instructions in appendix a for the xilinx kc705 based system. verilog code may be downloaded from the respective adc landing page. www.linear.com/LTC2123 channel 1 single-ended analog input optional fpga reference clock input optional fpga reference signal input optional sys_ref input for adc (sub class 1 only) single-ended device clock input optional sys_ref input for fpga (sub class 1 only) jumpers shown in their default positions 4v to 6v dc1974 f01 the dc1974 connects to kc705 via an fmc connector channel 2 single-ended analog input dc1974fa demo manual dc1974
3 hardware setup smas j1: aina C analog input for channel a C apply a signal to j1 from a 50? driver. filters are required for data sheet performance . j2: ainb C analog input for channel b C apply a signal to j2 from a 50? driver. filters are required for data sheet performance . j 3: dev clk C C encode clock input for single- ended clocks? C? by default the dc1974 is defined to accept a single-ended clock signal on j3. it can be modified to ac - cept a differential clock signal through j3 and j4. some component changes are required, see the encode clock section for more information. j4: dev clk + C encode clock input for differential sig - nals? C? by default the dc1974 is defined to accept a single-ended clock signal on j3. it can be modified to accept a differential clock signal through j3 and j4. some component changes are required, see the encode clock section for more information. j5 and j6: adc_sys_ref C jesd204b subclass 1 only C when testing the adc in subclass 1 operation a sys_ref input is required to synchronize the adc and fpga. apply a sys_ref signal to this input from a sys_ref driver board. this input drives the sys_ref of the adc. j11 and j12: fpga_sys_ref C jesd204b subclass 1 only C when testing the adc in subclass 1 operation a sys_ref input is required to synchronize the adc and fpga. apply a sys_ ref signal to this input from a sys_ ref driver board. this input drives the sys_ref of the fpga. j7 and j8: fpga_gbt_ref C this is an optional reference port for the fpga. it is used for testing purposes only. in the default configuration these smas are not used. j9 and j10: fpga_clk C this is an optional clock input port for the fpga. it is used for testing purposes only. in the default configuration these smas are not used. turrets v +: positive supply voltage for the adc and digital logic? C? this voltage feeds a regulator that supplies the proper voltages for the adc and buffers. the voltage range for this turret is 4v to 6v. the supply should be able to deliver 700ma of current. sense: optional reference voltage C this pin is connected directly to the sense pin of the adc. connecting sense to vdd selects the internal reference and a 0.66v input range. the same input voltage range can be achieved by applying an external 1.25v reference to sense. if no external voltage is supplied this pin will be pulled up to vdd through a 1k pull-up resistor. 1.8v out: optional 1.8v turret C this pin is connected directly to the vdd pin of the adc. it requires a supply that can deliver up to 500ma. driving this pin will shutdown the on board regulator. it can also be a test point to measure the voltage at the output of the regulators. gnd: ground connection C this demo board only has a single ground plane. this turret should be tied to the gnd terminal of the power supply being used. jumpers: jp1 eeprom: eeprom write protect. for factory use only. should be left in the enable (prog) position. jp2 sync: this jumper is provided to manually force the sync~ signal of the adc to a known value. by default, the resistors connecting this jumper are removed. if r20 and r21 are installed the sync jumper can be used to force sync~ high or low depending on the position of the jumper. position 0 is for low and 1 is for high. dc1974fa demo manual dc1974
4 if a kintex 7 fpga board is used to acquire data from the? dc1974, the kintex 7 fpga board must first be powered before applying 4 v to 6 v across the pins marked v+ and gnd on the dc1974. for more information about the kintex 7 board, please see the demo manual at www. xilinx. com. the dc1974 requires at least 4 v for proper operation. regulators on the board produce the voltages required for the adc and the required logic devices. the dc1974 requires up to 700ma. the dc1974 should not be removed or connected to the kintex 7 fpga board while power is applied. the dc2159 should also be connected to the kintex 7 board and the supplied mini usb cable should be con - nected to? the dc2159. the kintex 7 board should be powered on before? the mini usb connector is connected to the?dc2159. see figure 5 in appendix a. applying power and signals to the dc1974 demonstration circuit apply the analog input signal of interest to the sma con - nector on the dc1974 board marked j1 or j2. in the default setup, the dc1974 has a single sma input that is meant to be driven with a 50 source . the dc1974 is populated with an input network that has 50 characteristic imped - ance over a wide frequency range. this can be modified to produce different frequency responses as needed. al - though the input of the dc1974 is single-ended, there is a transformer on the board that translates the single-ended signal to a differential signal to drive the adc. analog input network in almost all cases, off board filters with good return loss will be required on the analog input of the dc1974 to produce data sheet snr. the off board filter should be located close to the input of the demo board to avoid reflections from impedance discontinuities at the driven end of a long transmission line. most filters do not present 50 outside the passband. in some cases, 3db to 10db pads may be required to make the filter look more like 50 to obtain low distortion. apply an encode clock to the sma connector on the dc1974 marked j3. by default, the dc1974 is configured to have a single-ended clock input. although the clock input of the dc1974 is single-ended, there is a transformer on the board that translates the single-ended signal to a dif - ferential signal to drive the adc. for the best noise performance , the encode input must be driven with a very low jitter signal generator source . the amplitude should be as large as possible up to 2v p-p or 10dbm. the dc1974 is designed to accept single-ended signals by default. to modify the dc1974 to accept a differential signal, remove c33, r44, r45 and r46. populate r49, r43, r48 and r47 with 0 resistors. drive the demo board with a differential signal on j3 and j4. these smas are positioned 0.5" apart to accommodate lt c differential clock boards. encode clock dc1974fa demo manual dc1974
5 the dc1974 is controlled by the pscope ? system soft - ware provided or downloaded from the linear technology website at http://www.linear.com/software/. if a kintex 7 fpga board and dc2159 were provided, follow the demo manual of these boards for proper setup. the kintex 7 fpga board will act as the data collection board and the dc2159 is used to connect the fpga to the computer. these boards both are designed to work seamlessly with pscope, linear technology s data col - lection software. to start the data collection software and if pscope.exe is installed (by default) at \program files\ lt c \pscope\, double click the pscope icon or bring up the run window under the start menu and browse to the pscope directory and select pscope. if the dc1974 is properly connected to the kintex 7 fpga board and the dc2159, pscope should automatically detect the dc1974 and configure itself accordingly. if necessary the procedure below explains how to manually configure pscope. under the configure menu, go to adc configuration... check the config manually box and use the following configuration options, shown in figure 2: manual configuration settings: bits: 14 alignment: 16 channs: 2 bipolar: unchecked positive-edge clk: unchecked if everything is hooked up properly, powered and a suit - able encode clock is present, clicking the collect button should result in time and frequency plots displayed in the pscope window. additional information and help for pscope is available in the kc705 guide and in the online help available within the pscope program itself. note: if a prbs error occurs hit connect again. this is a bug in the first version of the software. serial programming pscope has the ability to program the dc1974 board serially through the dc2159. there are several options available for the LTC2123 family that are only available through serial programming. pscope allows all of these features to be tested. these options are available by first clicking on the set demo bd options icon on the pscope toolbar (figure 3). this will bring up the menu shown in figure 4. software figure 2: adc configuration figure 3: pscope toolbar dc1974fa demo manual dc1974
6 this menu allows any of the options available for the LTC2123 to be programmed serially. the LTC2123 family has the following options: sleep mode C selects between normal operation and sleep mode. n off (default) C entire adc is powered and active. n on C the entire adc is powered down. nap mode C selects between normal operation and nap?mode. n off (default) C entire adc is powered and active. n on C the entire adc is put into nap mode. channel b power down C selects between normal opera - tion and powering down channel b. n off (default) C normal operation. n on C channel b is powered down. channel a power down C selects between normal opera - tion and powering down channel b. n off (default) C normal operation. n on C channel a is powered down. 2x clock C selects between a sample rate equal to the device clock, or device clock twice the sample rate. n off (default) C dev clk is equal to the sample rate. n on C dev clk is twice the sample rate. overflow C enables or disables the overflow bit in the output data. n disabled (default) C over flow bit is disabled . n enabled C overflow bit is enabled. duty cycle stabilizer C enables or disables duty cycle stabilizer. n stabilizer off ( default) C duty cycle stabilizer disabled. n stabilizer on C duty cycle stabilizer enabled. device id C sets the device id defined in jesd204b 8.3. default is 00000000, but can be set to whatever the user chooses. bank id C sets the bank id defined in jesd204b 8.3. de - fault is 0000, but can be set to whatever the user chooses. frames per multiframe C selects number of frames in each multiframe as defined in jesd204b 5.3.3.5. the user selects the number of desired frames per multiframe and pscope configures the adc accordingly. valid values for number of frames per multiframe are 9 to 32. figure 4: demo bd configuration options software dc1974fa demo manual dc1974
7 lane alignment sequence C enables or disables the lane alignment sequence. n enabled (default) C lane alignment sequence is enabled. n disabled - lane alignment sequence is disabled. lane alignment monitor C enables or disables the lane monitor sequence. n enabled ( default) C lane alignment monitor sequence is enabled. n disabled C lane alignment monitor sequence is disabled. frame alignment monitor C enables or disables the frame monitor sequence n enabled (default) C frame alignment monitor se - quence is enabled. n disabled C frame alignment monitor sequence is disabled. reset dividers (subclass 1 or 2 only) C enables or dis - ables sysref reset of dividers. n enabled ( default) C subclass 1 C enables the sysref reset of dividers. subclass 2 C enables sync~ reset of dividers. n disabled C subclass 1 C disables the sysref reset of dividers. subclass 2 C disables sync~ reset of dividers. scrambling C enables or disables the scrambling of the output data. n disabled (default) C scrambling is disabled. n enabled C scrambling is enabled. alert mode de-arm length (subclass 1 only) C selects the de-arming length in multiframe periods to trigger the alert in subclass 1. valid values are 1 to 8. alert mode (subclass 1 only) C enables or disables the alert mode. n disabled (default) C alert mode is disabled. n enabled C alert mode is enabled. tx sync C enables or disables transmitter induced syn - chronization. n disabled (default) C transmitter induced synchro - nization is?disabled. n enabled - transmitter induced synchronization is?enabled. test pattern C selects the data presented at the output of the adc normal adc data (default) C the data that is sampled by the input of the adc k28.5 pattern C a repeating sync comma. k28.7 pattern C 1111100000. d21.5 pattern C 1010101010. prbs15 pattern C a pseudorandom bit sequence pat - tern described by 1 + x 14 + x 15 . lane alignment sequence C the lane alignment se - quence is transmitted according to tables 3a to 3h from the datasheet. test samples sequence C the test samples are repeat - edly transmitted according to tables 4a to 4b from the datasheet. modified r pat pattern C a modified rpat pattern as described in ieee std. 802.3-2008 annex 48a. cml output magnitude C magnitude of the cml out - put?signals. value selections are: 10ma (250mv) default 12ma (300mv) 14ma (350mv) 16ma (400mv) once the desired settings are selected hit ok and pscope will automatically update the register of the device on the dc1974 demo board . software dc1974fa demo manual dc1974
8 xilinx kc705 based evaluation system the demonstration system for the LTC2123 family consists of the dc1974, a xilinx kc705 fpga evaluation board, a dc2159 usb communication board and a host pc running the pscope software. complete systems that ship from linear technology will have the kc705 board configured to automatically load the default subclass 0 fpga image from the onboard configuration eeprom. the procedure for bringing up the system is as follows: 1) if the boards were obtained separately, assemble them as shown in figure 5 (fmc connectors are fragile, make sure they are properly aligned before seating.) 2) connect power supply to the kc705 board and turn on the power switch. if the assembled system was obtained from linear technology , the subclass 0 image will load automatically from the onboard confguration memory . 3) boards not obtained from linear technology will need to be confgured as described in the alternate fpga confguration section. 4) apply power, encode clock and analog input signals to the dc1974 board. 5) verify that pscope software is installed. connect dc2159 to the host pc with a usb-mini cable. driver installation will start automatically and pscope will recognize the dc1974 when installation fnishes. note: power must be applied to the kc705 board when the usb cable is connected or the driver installation will not complete properly. alternate fpga configuration kc705 boards not obtained from linear technology will need to be configured via jtag. fpga images are located in the pscope installation directory in the fpga_images folder. connect a usb micro cable to the jtag usb con - nector on the kc705 board and use a xilinx tool such as impact to load the subclass 0, 2 lane bitfile. once the fpga is configured, remove the usb cable and exit the software. (the onboard jtag adapter and the dc2159 usb communication board use the same usb controller and they may interfere with one another.) appendix a dc1974fa demo manual dc1974
9 5. connect dc2159 to pc 1. assemble boards 4. power-up dc1974, turn on clock and analog inputs 3. configure fpga via jtag (if necessary), then remove usb cable 2. power-up kc705 dc1974 f05 figure 5. kc705 based demonstration system appendix a dc1974fa demo manual dc1974
10 parts list item qty reference part description manufacturer / part # required circuit components 1 2 c1, c2 cap., x5r, 1f, 10v, 10%, 0402 avx , 0402zd105 kat 2a 2 1 c3 cap., tant, 100f, 10v, 10%, 6032 avx , tajw107k010rnj 3 1 c4 cap., x7r, 47f,10v, 10%, 1210 murata , grm32er71a476ke15l 4 4 c5, c11, c25, c26 cap., x5r, 2.2f, 10v, 20%, 0603 avx , 0603zd225 mat 2a 5 7 c6, c33-c35, c50-c52 cap., x7r, 0.01f, 16v, 10%, 0402 avx , 0402yc103 kat 2a 6 1 c7 cap., x5r, 10f, 6.3v, 20%, 0805 avx , 08056d106 mat 2a 7 22 c10, c12-c24, c27-c32, c41, c53 cap., x5r, 0.1f, 10v, 10%, 0402 avx , 0402zd104 kat 2a 8 4 c37, c38, c39, c40 cap., c0g, 47pf, 16v, 10%, 0402 avx , 0402ya 470 kat 2a 9 8 c42-c49 cap., x7r, 1000pf, 50v, 10%, 0402 avx , 04025c102 kat 2a 10 4 e1, e2, e3, e4 testpoint, turret, 0.094" mill-max, 2501-2-00-80-00-00-07-0 11 2 jp1, jp2 header, hd1x3-079 sullins, nrpn031 paen-rc 12 10 j1-j6, j9-j12 conn., sma 50, edge-launch ef johnson, 142-0701-851 13 0 j7, j8 ( opt ) conn., sma 50, edge-launch ef johnson, 142-0701-851 14 1 j13 conn., bga 40x10 samtec, seam-40-02.0-s-10-2-a-k-tr 15 1 l1 res., chip, 0, 1206 vishay , crcw12060000z0ea 16 1 l2 ind., ferrite bead, 33, 1206 murata , blm31pg330sn1l 17 0 l3 res., 1206 opt 18 2 r1,r59 res., chip , 3.01k, 1/16w, 1%, 0402 vishay , crcw04023k01fked 19 1 r2 res., chip, 10k, 1/16w, 1%, 0402 vishay , crcw040210k0fked 20 1 r4 res., chip, 182k, 1/16w, 1%, 0402 vishay , crcw0402182kfked 21 4 r5, r24, r25, r58 res., chip, 1k, 1/16w, 1%, 0402 nic, nrc04f1001trf 22 10 r6-r11, r32-r35 res., chip, 24.9, 1/16w, 1%, 0402 vishay , crcw040224r9fked 23 11 r12, r13, r15, r16, r18, r39, r40, r44, r45, r46, r57 res., chip, 0, 1/16w, 0402 nic, nrc04z0trf 24 5 r14, r17, r41, r56, r61 res., chip, 100, 1/16w, 1%, 0402 nic, nrc04f1000trf 25 0 r19-r23, r42, r43, r48-r53, r54, r55, r60 res., 0402 opt 26 2 r26, r29 res., chip, 20, 1/16w, 1%, 0402 nic, nrc04f20r0trf 27 2 r27, r28 res., chip, 49.9, 1/16w, 1%, 0402 vishay , crcw040249r9fked 28 2 r30, r31 res., chip, 300, 1/16w, 1%, 0402 nic, nrc04f3000trf 29 3 r36, r37,r38 res., chip, 4.99k, 1/16w, 1%, 0402 vishay , crcw04024k99fked 30 5 r47, r62,r63,r64,r65 res., chip, 4.99, 1/16w, 1%, 0402 nic, nrc04f4r99trf 31 2 r66, r67 res., chip, 100, 1/20w, 1%, 0201 nic, nrc02f1000trf 32 3 t1, t2, t3 xfmr., maba-007159-000000 m/a-com, maba-007159-000000 33 1 u2 i.c., lt3080edd#pbf, dfn 3x3 linear tech., lt3080edd#pbf 34 1 u3 i.c., lt1763cde-3.3#pbf, dfn12de-4x3 linear tech., lt1763 cde-3.3#pbf 35 1 u6 i.c. eeprom 32kbit 400khz, tssop8 microchip, 24lc32a-i/st dc1974fa demo manual dc1974
11 item qty reference part description manufacturer / part # 36 1 u7 i.c., nc7wz14p6x, sc70-6 fairchild semi., nc7wz14p6x 37 1 u9 i.c., ltc6957idd-2#pbf, dfn12dd-3x3 linear tech., ltc6957idd-2#pbf 38 1 shunts for jp1 & jp2 shunt, 0.079" center samtec, 2sn-bk-g 39 0 mh1, mh2 screw, m3 thread, #4-40x5/8" keystone, 29316 (do not install) 40 0 mh1, mh2 stand -off, alum., m3 thread, 5.0 hex, #4-40x1" keystone, 24438 (do not install) 41 2 stencils stencils (top & bottom) stencil dc1974a-3 dc1974a-b required circuit components 1 1 dc1974a general bom 2 1 u1 i.c., 14-bit, 250msps, qfn48uk-7x7 linear tech., LTC2123iuk#pbf dc1974a-c required circuit components 1 1 dc1974a general bom 2 1 u1 i.c., 14-bit, 170msps, qfn48uk-7x7 linear tech., ltc2122iuk#pbf parts list dc1974fa demo manual dc1974
12 schematic diagram 5 5 4 4 3 3 2 2 1 1 d d c c b b a a assy LTC2123iuk-14 u1 ltc2122iuk-14 * 250 170 msps gnd v+ 4v - 6v all capacitors are in microfarads, 0402. notes: unless otherwise specified 2. install shunts as shown. 1. all resistors are in ohms, 0402. -bit 14 14 -b -c c42 - c49 1000pf sync 0 1 cml* connections are 50 ohms 3. r18 is optional at the final version. sense ainb- ainb+ aina- aina+ vcm clk- clk+ v+ +3.3v v+ vdd vdd vdd vdd vdd vdd vdd ovdd ovdd vdd ovdd ovdd vdd vdd vdd +3.3v vdd +3.3v +3.3v cmlb1_n cmlb1_p sync_n sync_p cmlb2_n cmlb2_p cmla2_p cmla1_n cmla1_p cmla2_n of+ of- cs sck sdi sdo fpga_clk_p fpga_clk_n revision history description date approved eco rev clarence m. production 5 1 - 5 2 - 2 0 3 __ revision history description date approved eco rev clarence m. production 5 1 - 5 2 - 2 0 3 __ revision history description date approved eco rev clarence m. production 5 1 - 5 2 - 2 0 3 __ size date: . v e r . o n c i sheet of title: approvals pcb des. app eng. technology fax: (408)434-0507 milpitas, ca 95035 phone: (408)432-1900 1630 mccarthy blvd. ltc confidential-for customer use only customer notice linear technology has made a best effort to design a circuit that meets customer-supplied specifications; however, it remains the customer's responsibility to verify proper and reliable operation in the actual application. component substitution and printed circuit board layout may significantly affect circuit performance or reliability. contact linear technology applications engineering for assistance. this circuit is proprietary to linear technology and schematic supplied for use with linear technology parts. scale = none www.linear.com 3 demo circuit 1974a wednesday, february 25, 2015 1 2 n/a ltc212xiuk family kim t. clarence m. dual 14-bit high speed adc with jesd204b serial outputs size date: . v e r . o n c i sheet of title: approvals pcb des. app eng. technology fax: (408)434-0507 milpitas, ca 95035 phone: (408)432-1900 1630 mccarthy blvd. ltc confidential-for customer use only customer notice linear technology has made a best effort to design a circuit that meets customer-supplied specifications; however, it remains the customer's responsibility to verify proper and reliable operation in the actual application. component substitution and printed circuit board layout may significantly affect circuit performance or reliability. contact linear technology applications engineering for assistance. this circuit is proprietary to linear technology and schematic supplied for use with linear technology parts. scale = none www.linear.com 3 demo circuit 1974a wednesday, february 25, 2015 1 2 n/a ltc212xiuk family kim t. clarence m. dual 14-bit high speed adc with jesd204b serial outputs size date: . v e r . o n c i sheet of title: approvals pcb des. app eng. technology fax: (408)434-0507 milpitas, ca 95035 phone: (408)432-1900 1630 mccarthy blvd. ltc confidential-for customer use only customer notice linear technology has made a best effort to design a circuit that meets customer-supplied specifications; however, it remains the customer's responsibility to verify proper and reliable operation in the actual application. component substitution and printed circuit board layout may significantly affect circuit performance or reliability. contact linear technology applications engineering for assistance. this circuit is proprietary to linear technology and schematic supplied for use with linear technology parts. scale = none www.linear.com 3 demo circuit 1974a wednesday, february 25, 2015 1 2 n/a ltc212xiuk family kim t. clarence m. dual 14-bit high speed adc with jesd204b serial outputs j9 fpga_clk_n sma j9 fpga_clk_n sma j5 adc_sys_ref_n sma j5 adc_sys_ref_n sma r46 0 r46 0 r22 opt r22 opt r12 0 r12 0 r1 3.01k r1 3.01k l1 0 ohm res 1206 l1 0 ohm res 1206 c50 0.01uf c50 0.01uf e3 sense e3 sense c5 2.2uf 0603 c5 2.2uf 0603 e4 1.8v out e4 1.8v out r48 opt r48 opt r67 100 0201 r67 100 0201 r29 20 r29 20 j10 fpga_clk_p sma j10 fpga_clk_p sma j6 adc_sys_ref_p sma j6 adc_sys_ref_p sma r25 1k r25 1k r44 0 r44 0 r39 0 r39 0 r40 0 r40 0 r41 100 r41 100 t3 maba-007159-000000 t3 maba-007159-000000 5 4 3 1 2 r47 4.99 r47 4.99 r13 0 r13 0 r66 100 0201 r66 100 0201 r20 opt r20 opt r10 45.3 r10 45.3 c11 2.2uf 0603 c11 2.2uf 0603 r14 100 r14 100 r27 49.9 r27 49.9 r54 opt r54 opt t1 maba-007159-000000 t1 maba-007159-000000 5 4 3 1 2 r64 4.99 r64 4.99 r50 opt r50 opt e1 e1 c14 0.1uf c14 0.1uf r28 49.9 r28 49.9 c24 0.1uf c24 0.1uf r7 45.3 r7 45.3 c34 0.01uf c34 0.01uf r49 opt r49 opt c7 10uf 0805 c7 10uf 0805 c26 2.2uf 0603 c26 2.2uf 0603 u1 * qfn48uk-7x7 u1 * qfn48uk-7x7 vdd 1 gnd 2 aina+ 3 aina- 4 sense 5 vref 6 vcm 7 gnd 8 ainb- 9 ainb+ 10 gnd 11 vdd 12 vdd 1 3 g n d 1 4 devclk- 1 5 devclk+ 1 6 g n d 1 7 sysref_p 1 8 sysref_n 1 9 g n d 2 0 sync_p 2 1 sync_n 2 2 vdd 2 3 vdd 2 4 ovdd 25 ovdd 26 cmlb2_n 27 cmlb2_p 28 cmlb1_n 29 cmlb1_p 30 cmla1_n 31 cmla1_p 32 cmla2_n 33 cmla2_p 34 ovdd 35 ovdd 36 vdd 3 7 vdd 3 8 dnc 3 9 dnc 4 0 o f n - 4 1 o f n + 4 2 sdo 4 3 sdi 4 4 sck 4 5 c s 4 6 g n d 4 7 vdd 4 8 g n d 4 9 l2 33 ohm fb 1206 l2 33 ohm fb 1206 t2 maba-007159-000000 t2 maba-007159-000000 5 4 3 1 2 c6 0.01uf c6 0.01uf c35 0.01uf c35 0.01uf c4 47uf 1210 c4 47uf 1210 c51 0.01uf c51 0.01uf u3 lt1763cde-3.3 u3 lt1763cde-3.3 out 2 out 3 e p 1 3 shdn 8 nc 9 g n d 7 in 10 in 11 sense 5 nc 4 nc 1 nc 12 byp 6 c32 0.1uf c32 0.1uf r16 0 r16 0 r30 300 r30 300 j2 ainb sma j2 ainb sma c15 0.1uf c15 0.1uf c53 0.1uf c53 0.1uf r56 100 r56 100 c17 0.1uf c17 0.1uf l3 opt 1206 l3 opt 1206 c19 0.1uf c19 0.1uf c13 0.1uf c13 0.1uf c25 2.2uf 0603 c25 2.2uf 0603 c16 0.1uf c16 0.1uf r18 0 [3] r18 0 [3] r21 opt r21 opt c18 0.1uf c18 0.1uf r60 opt r60 opt c27 0.1uf c27 0.1uf r2 10k r2 10k c33 0.01uf c33 0.01uf j1 aina sma j1 aina sma r63 4.99 r63 4.99 u9 ltc6957idd-2 u9 ltc6957idd-2 gnd 5 in- 4 in+ 3 v+ 2 filta 1 out1- 10 out2- 9 out2+ 8 sd2 7 filtb 6 out1+ 11 sd1 12 e p 1 3 r45 0 r45 0 c23 0.1uf c23 0.1uf + c3 100uf 10v 6032 + c3 100uf 10v 6032 r6 45.3 r6 45.3 c52 0.01uf c52 0.01uf r24 1k r24 1k r4 182k r4 182k gnd vcc u7 nc7wz14p6x gnd vcc u7 nc7wz14p6x 1 6 4 3 5 2 j4 devclk+ sma j4 devclk+ sma c10 0.1uf c10 0.1uf r11 45.3 r11 45.3 c31 0.1uf c31 0.1uf jp2 jp2 1 3 2 c30 0.1uf c30 0.1uf r15 0 r15 0 c2 1uf c2 1uf r5 1k r5 1k c21 0.1uf c21 0.1uf r42 opt r42 opt r26 20 r26 20 c28 0.1uf c28 0.1uf r23 opt r23 opt r62 4.99 r62 4.99 e2 e2 r9 24.9 r9 24.9 r8 24.9 r8 24.9 r43 opt r43 opt r17 100 r17 100 r19 opt r19 opt c20 0.1uf c20 0.1uf c1 1uf c1 1uf c12 0.1uf c12 0.1uf r65 4.99 r65 4.99 r61 100 r61 100 r55 opt r55 opt r52 opt r52 opt r31 300 r31 300 c22 0.1uf c22 0.1uf r53 opt r53 opt lt3080edd u2 lt3080edd u2 out 1 out 2 out 3 set 4 vctrl 5 nc 6 in 7 in 8 ep 9 j3 devclk- sma j3 devclk- sma c29 0.1uf c29 0.1uf r51 opt r51 opt dc1974fa demo manual dc1974
13 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. schematic diagram 5 5 4 4 3 3 2 2 1 1 d d c c b b a a eeprom wp prog cs_fmc scl sda sck_fmc sdi_fmc sdo_fmc 3p3vaux vdd +3.3v cs sdo sdi sck cmla2_p cmla2_n cmlb1_n cmlb1_p cmlb2_n cmlb2_p cmla1_p cmla1_n sync_p sync_n of+ of- fpga_clk_p fpga_clk_n size date: . v e r . o n c i sheet of title: approvals pcb des. app eng. technology fax: (408)434-0507 milpitas, ca 95035 phone: (408)432-1900 1630 mccarthy blvd. ltc confidential-for customer use only customer notice linear technology has made a best effort to design a circuit that meets customer-supplied specifications; however, it remains the customer's responsibility to verify proper and reliable operation in the actual application. component substitution and printed circuit board layout may significantly affect circuit performance or reliability. contact linear technology applications engineering for assistance. this circuit is proprietary to linear technology and schematic supplied for use with linear technology parts. scale = none www.linear.com 3 demo circuit 1974a wednesday, february 25, 2015 2 2 n/a ltc212xiuk family kim t. clarence m. dual 14-bit high speed adc with jesd204b serial outputs size date: . v e r . o n c i sheet of title: approvals pcb des. app eng. technology fax: (408)434-0507 milpitas, ca 95035 phone: (408)432-1900 1630 mccarthy blvd. ltc confidential-for customer use only customer notice linear technology has made a best effort to design a circuit that meets customer-supplied specifications; however, it remains the customer's responsibility to verify proper and reliable operation in the actual application. component substitution and printed circuit board layout may significantly affect circuit performance or reliability. contact linear technology applications engineering for assistance. this circuit is proprietary to linear technology and schematic supplied for use with linear technology parts. scale = none www.linear.com 3 demo circuit 1974a wednesday, february 25, 2015 2 2 n/a ltc212xiuk family kim t. clarence m. dual 14-bit high speed adc with jesd204b serial outputs size date: . v e r . o n c i sheet of title: approvals pcb des. app eng. technology fax: (408)434-0507 milpitas, ca 95035 phone: (408)432-1900 1630 mccarthy blvd. ltc confidential-for customer use only customer notice linear technology has made a best effort to design a circuit that meets customer-supplied specifications; however, it remains the customer's responsibility to verify proper and reliable operation in the actual application. component substitution and printed circuit board layout may significantly affect circuit performance or reliability. contact linear technology applications engineering for assistance. this circuit is proprietary to linear technology and schematic supplied for use with linear technology parts. scale = none www.linear.com 3 demo circuit 1974a wednesday, february 25, 2015 2 2 n/a ltc212xiuk family kim t. clarence m. dual 14-bit high speed adc with jesd204b serial outputs r32 24.9 r32 24.9 j12 fpga_sys_ref_n sma j12 fpga_sys_ref_n sma j13j seam-10x40pin j13j seam-10x40pin gnd j1 clk1_c2m_p j2 clk1_c2m_n j3 gnd j4 gnd j5 ha03_p j6 ha03_n j7 gnd j8 ha07_p j9 ha07_n j10 gnd j11 ha11_p j12 ha11_n j13 gnd j14 ha14_p j15 ha14_n j16 gnd j17 ha18_p j18 ha18_n j19 gnd j20 ha22_p j21 ha22_n j22 gnd j23 hb01_p j24 hb01_n j25 gnd j26 pb07_p j27 hb07_n j28 gnd j29 hb11_p j30 hb11_n j31 gnd j32 hb15_p j33 hb15_n j34 gnd j35 hb18_p j36 hb18_n j37 gnd j38 vio_b_m2c j39 gnd j40 r33 24.9 r33 24.9 r37 4.99k r37 4.99k j13e seam-10x40pin j13e seam-10x40pin gnd e1 ha01_p_cc e2 ha01_n_cc e3 gnd e4 gnd e5 ha05_p e6 ha05_n e7 gnd e8 ha09_p e9 ha09_n e10 gnd e11 ha13_p e12 ha13_n e13 gnd e14 ha16_p e15 ha16_n e16 gnd e17 ha20_p e18 ha20_n e19 gnd e20 hb03_p e21 hb03_n e22 gnd e23 hb05_p e24 hb05_n e25 gnd e26 hb09_p e27 hb09_n e28 gnd e29 hb13_p e30 hb13_n e31 gnd e32 hb21_p e33 hb21_n e34 gnd e35 hb20_p e36 hb20_n e37 gnd e38 vadj e39 gnd e40 sck sck j13a seam-10x40pin j13a seam-10x40pin gnd a1 dp1_m2c_p a2 dp1_m2c_n a3 gnd a4 gnd a5 dp2_m2c_p a6 dp2_m2c_n a7 gnd a8 gnd a9 dp3_m2c_p a10 dp3_m2c_n a11 gnd a12 gnd a13 dp4_m2c_p a14 dp4_m2c_n a15 gnd a16 gnd a17 dp5_m2c_p a18 dp5_m2c_n a19 gnd a20 gnd a21 dp1_c2m_p a22 dp1_c2m_n a23 gnd a24 gnd a25 dp2_c2m_p a26 dp2_c2m_n a27 gnd a28 gnd a29 dp3_c2m_p a30 dp3_c2m_n a31 gnd a32 gnd a33 dp4_c2m_p a34 dp4_c2m_n a35 gnd a36 gnd a37 dp5_c2m_p a38 dp5_c2m_n a39 gnd a40 c40 47pf c40 47pf j7 fpga_gbt_ref_p sma opt j7 fpga_gbt_ref_p sma opt c39 47pf c39 47pf j13k seam-10x40pin j13k seam-10x40pin vref_b_m2c k1 gnd k2 gnd k3 clk1_m2c_p k4 clk1_m2c_n k5 gnd k6 ha02_p k7 ha02_n k8 gnd k9 ha06_p k10 ha06_n k11 gnd k12 ha10_p k13 ha10_n k14 gnd k15 ha17_p_cc k16 ha17_n_cc k17 gnd k18 ha21_p k19 ha21_n k20 gnd k21 ha23_p k22 ha23_n k23 gnd k24 hb00_p_cc k25 hb00_n_cc k26 gnd k27 hb06_p_cc k28 hb06_n_cc k29 gnd k30 hb10_p k31 hb10_n k32 gnd k33 hb14_p k34 hb14_n k35 gnd k36 hb17_p_cc k37 hb17_n_cc k38 gnd k39 vio_b_m2c k40 r36 4.99k r36 4.99k sdo sdo j13f seam-10x40pin j13f seam-10x40pin pg_m2c f1 gnd f2 gnd f3 ha00_p_cc f4 ha00_n_cc f5 gnd f6 ha04_p f7 ha04_n f8 gnd f9 ha08_p f10 ha08_n f11 gnd f12 ha12_p f13 ha12_n f14 gnd f15 ha15_p f16 ha15_n f17 gnd f18 ha19_p f19 ha19_n f20 gnd f21 hb02_p f22 hb02_n f23 gnd f24 hb04_p f25 hb04_n f26 gnd f27 hb08_p f28 hb08_n f29 gnd f30 hb12_p f31 hb12_n f32 gnd f33 hb16_p f34 hb16_n f35 gnd f36 hb19_p f37 hb19_n f38 gnd f39 vadj f40 j8 fpga_gbt_ref_n sma opt j8 fpga_gbt_ref_n sma opt jp1 jp1 1 3 2 gnd gnd r58 1k r58 1k j13b seam-10x40pin j13b seam-10x40pin res1 b1 gnd b2 gnd b3 dp9_m2c_p b4 dp9_m2c_n b5 gnd b6 gnd b7 dp8_m2c_p b8 dp8_m2c_n b9 gnd b10 gnd b11 dp7_m2c_p b12 dp7_m2c_n b13 gnd b14 gnd b15 dp6_m2c_p b16 dp6_m2c_n b17 gnd b18 gnd b19 gbtclk1_m2c_p b20 gbtclk1_m2c_n b21 gnd b22 gnd b23 dp9_c2m_p b24 dp9_c2m_n b25 gnd b26 gnd b27 dp8_c2m_p b28 dp8_c2m_n b29 gnd b30 gnd b31 dp7_c2m_p b32 dp7_c2m_n b33 gnd b34 gnd b35 dp6_c2m_p b36 dp6_c2m_n b37 gnd b38 gnd b39 res0 b40 c37 47pf c37 47pf j13g seam-10x40pin j13g seam-10x40pin gnd g1 clk0_c2m_p g2 clk0_c2m_n g3 gnd g4 gnd g5 la00_p_cc g6 la00_n_cc g7 gnd g8 la03_p g9 la03_n g10 gnd g11 la08_p g12 la08_n g13 gnd g14 la12_p g15 la12_n g16 gnd g17 la16_p g18 la16_n g19 gnd g20 la20_p g21 la20_n g22 gnd g23 la22_p g24 la22_n g25 gnd g26 la25_p g27 la25_n g28 gnd g29 la29_p g30 la29_n g31 gnd g32 la31_p g33 la31_n g34 gnd g35 la33_p g36 la33_n g37 gnd g38 vadj g39 gnd g40 r57 0 r57 0 sdi sdi j13c seam-10x40pin j13c seam-10x40pin gnd c1 dp0_c2m_p c2 dp0_c2m_n c3 gnd c4 gnd c5 dp0_m2c_p c6 dp0_m2c_n c7 gnd c8 gnd c9 la06_p c10 la06_n c11 gnd c12 gnd c13 la10_p c14 la10_n c15 gnd c16 gnd c17 la14_p c18 la14_n c19 gnd c20 gnd c21 la18_p_cc c22 la18_n_cc c23 gnd c24 gnd c25 la27_p c26 la27_n c27 gnd c28 gnd c29 scl c30 sda c31 gnd c32 gnd c33 ga0 c34 12p0v c35 gnd c36 12p0v c37 gnd c38 3p3v c39 gnd c40 r35 24.9 r35 24.9 r59 3.01k r59 3.01k r34 24.9 r34 24.9 cs cs j13h seam-10x40pin j13h seam-10x40pin vref_a_m2c h1 prsnt_m2c_n h2 gnd h3 clk0_m2c_p h4 clk0_m2c_n h5 gnd h6 la02_p h7 la02_n h8 gnd h9 la04_p h10 la04_n h11 gnd h12 la07_p h13 la07_n h14 gnd h15 la11_p h16 la11_n h17 gnd h18 la15_p h19 la15_n h20 gnd h21 la19_p h22 la19_n h23 gnd h24 la21_p h25 la21_n h26 gnd h27 la24_p h28 la24_n h29 gnd h30 la28_p h31 la28_n h32 gnd h33 la30_p h34 la30_n h35 gnd h36 la32_p h37 la32_n h38 gnd h39 vadj h40 c41 0.1uf c41 0.1uf r38 4.99k r38 4.99k j13d seam-10x40pin j13d seam-10x40pin pg_c2m d1 gnd d2 gnd d3 gbtclk0_m2c_p d4 gbtclk0_m2c_n d5 gnd d6 gnd d7 la01_p_cc d8 la01_n_cc d9 gnd d10 la05_p d11 la05_n d12 gnd d13 la09_p d14 la09_n d15 gnd d16 la13_p d17 la13_n d18 gnd d19 la17_p_cc d20 la17_n_cc d21 gnd d22 la23_p d23 la23_n d24 gnd d25 la26_p d26 la26_n d27 gnd d28 tck d29 tdi d30 tdo d31 3p3vaux d32 tms d33 trst_n d34 ga1 d35 3p3v d36 gnd d37 3p3v d38 gnd d39 3p3v d40 c38 47pf c38 47pf eeprom array u6 24lc32a eeprom array u6 24lc32a sda 5 vcc 8 a0 1 a1 2 a2 3 g n d 4 wp 7 scl 6 j11 fpga_sys_ref_p sma j11 fpga_sys_ref_p sma dc1974fa demo manual dc1974
14 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2014 lt 0315 rev a ? printed in usa demonstration board important notice linear technology corporation (ltc) provides the enclosed product(s) under the following as is conditions: this demonstration board (demo board) kit being sold or provided by linear technology is intended for use for engineering development or evaluation purposes only and is not provided by ltc for commercial use. as such, the demo board herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. as a prototype, this product does not fall within the scope of the european union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. if this evaluation kit does not meet the specifications recited in the demo board manual the kit may be returned within 30 days from the date of delivery for a full refund. the foregoing warranty is the exclusive warranty made by the seller to buyer and is in lieu of all other warranties, expressed, implied, or statutory, including any warranty of merchantability or fitness for any particular purpose. except to the extent of this indemnity, neither party shall be liable to the other for any indirect, special, incidental, or consequential damages. the user assumes all responsibility and liability for proper and safe handling of the goods. further, the user releases ltc from all claims arising from the handling or use of the goods. due to the open construction of the product, it is the users responsibility to take any and all appropriate precautions with regard to electrostatic discharge. also be aware that the products herein may not be regulatory compliant or agency certified (fcc, ul, ce, etc.). no license is granted under any patent right or other intellectual property whatsoever . ltc assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. ltc currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. please read the demo board manual prior to handling the product. persons handling this product must have electronics training and observe good laboratory practice standards. common sense is encouraged. this notice contains important safety information about temperatures and voltages. for further safety concerns, please contact a ltc application engineer. mailing address: linear technology 1630 mccarthy blvd. milpitas, ca 95035 copyright ? 2004, linear technology corporation dc1974fa demo manual dc1974

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